1. Field of the Invention
This invention relates to circuitry for locking internally-generated system clock signals of a computer system to function with externally-provided clock signals and, more particularly, to methods and apparatus for locking internally-generated clock signals to function with externally-provided clock signals which may vary over an extremely wide range of frequencies.
2. History of the Prior Art
When a computer system functions with an external peripheral device, it must utilize data provided by that external device. In order to use that data, it must receive not only the data but the clock signal which is used to distinguish the elements of the data signal train one from another. To derive meaning from the elements of the data signal train, a computer generates internal clock signals at the same frequency as the clock frequency of the peripheral device supplying the data. If each pulse of the internal clock train begins and ends at the same time as do the pulses of the external clock train, the data signals may be properly interpreted.
However, because the substrates of the integrated circuits upon which circuit elements are placed differ, because the circuits operate in different environments, and because the distances conductors must traverse from the source of the clock signals to the devices using the clock signals differ and exhibit different resistance and capacitance, the internal clock signals so generated may start and end at different points in time than do the external clock signals. Basically, the circuitry through which the clock signals are distributed to the circuit elements provides undesirable delay which causes the internal clock signals to reach the circuit elements delayed by some time. In order to make sure that the clock signals reach all of the elements which they affect at essentially the same time, the conductors carrying the clock signals are made, as nearly as possible, to have the same length. The typical manner in which this is accomplished is by branching the circuitry like a tree from the original source of the clock signals to the devices using the clock signals. Consequently, such circuitry is often referred to as a clock tree.
Thus, the internal clock signals generated from external clock signals are delayed (exhibit clock skew). When clock frequencies become very high so that the time during which data signals are present is quite short, clock skew becomes very significant. To eliminate clock skew, a typical computer will, therefore, sample the incoming clock signals and provide internal system clock signals the pulses of which are phase-locked (when measured at the devices using the clock signals) to the external clock signals. In this manner, both the peripheral device and the system operate at the same clock frequency so the externally provided data signals mean the same thing to the system as they do to the peripheral device.
Normally, this is not too difficult to accomplish. However, modern desktop computers are being designed as so-called "multimedia" stations in which television, stereophonic sound, and many other sources are all to be used to provide input signals. The requirement that a computer system operate with television and real time signals tends to force the internal frequency of the system to be quite high so that it can handle the copious amounts of information presented in those media. Many of the peripheral devices used for such multimedia functions themselves operate at quite high clock frequencies. On the other hand, many useful and proven peripheral devices function at much lower clock frequencies. Thus, a modern computer may have input signals arriving from peripheral devices which function on clock signals which vary from one megahertz to fifty megahertz. Providing internal system clock signals for such a range of frequencies and locking those internal clock signals to all of the external clocks over such a wide range creates a monumental problem.
For example, in order to assure that a peripheral device and a system operate on the same clock signals, a phase-locked loop circuit is normally provided. This circuitry may be analog or digital in nature, but the preference is for a digital circuit which can be placed in the same integrated circuit with other circuits and may conceivably use standard circuit layouts. To create a digital phase-locked loop circuit to synchronize the pulses of internal clock signals to external clock signals, circuitry of some sort for providing a delay must be used. Typically this circuitry provides a single delay line that generates a delay which when added to the clock skew delay equals one cycle of clock operation. The clock skew delay tends to be only a small part of the total clock period so that the internal clock signals actually operate approximately one full cycle behind the external clock signals. The phase of the signals provided through the delay line and the clock tree is compared at the device using the signal to the phase of the original clock signals, and the delay is adjusted to make the phases identical.
In implementing such digital circuitry as an integrated circuit, a string of inverters is typically used to provide the single adjustable delay line. If the delay is very brief as it would be in dealing with external clock signals of fifty megahertz, then the circuitry for providing the delay might utilize a reasonable number of inverter elements such as one thousand. On the other hand, the string of inverters necessary to provide a delay for an external clock signals operating at one megahertz would be fifty times as large. Such a great number of circuit elements will render a delay circuit impractically large and expensive.